sy100ep14au 2.5v/3.3v 1:5 lvpecl/lvecl/hstl 2ghz clock driver with 2:1 differential input mux micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com june 2010 m9999-061110-a hbwhelp@micrel.com or (408) 955-1690 general description the sy100ep14au is a high-speed, 2ghz differential pecl/ecl 1:5 fanout buffer optimized for ultra-low skew applications. within device skew is guaranteed to be less than 25ps over temperature and supply voltage. the wide supply voltage operation allows this fanout buffer to operate in 2.5v and 3.3v systems. a v bb reference is included for single-supply or ac-coupled pecl/ecl input applications, thus eliminati ng resistor networks. when interfacing to a single-ended or ac-coupled pecl/ecl input signal, connect the v bb pin to the unused /clk pin, and bypass the pin to v cc through a 0.01f capacitor. the sy100ep14au features a 2:1 input mux, making it an ideal solution for redundant clock switchover applications. if only one input pair is used, the other pair may be left floating. in addition, this device includes a synchronous enable pin that forc es the outputs into a fixed logic state. enable or disabl e state is initiated only after the outputs are in a low state, thus eliminating the possibility of a ?runt? clock pulse. the sy100ep14au i/o are fully differential and 100k ecl compatible. differential 10k ecl logic can interface directly into the sy100ep14au inputs. the sy100ep14au is part of micrel?s high-speed clock synchronization family. for ap plications that require a different i/o combination, consult the micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators. data sheets and support documentation can be found on micrel?s web site at: www.micrel.com . features ? guaranteed ac parameters over temp/voltage: ? >2ghz f max ? <25ps within-device skew ? <250ps tr/tf time ? <550ps prop delay ? 2:1 differential mux input ? unique, patented mux input isolation design minimizes adjacent channel crosstalk ? flexible supply voltage: 2.5v/3.3v ? wide operating temperature range: -40c to +85c ? v bb reference for single-ended or ac-coupled pecl inputs ? 100k ecl compatible outputs ? inputs accept pecl/lvpecl/ecl/hstl logic ? 75k ? internal input pull-down resistors ? available in a 20-pin tssop package applications ? sonet clock and data distribution ? fibre channel clock and data distribution ? ethernet clock and data distribution
micrel, inc. sy100ep14au june 2010 2 m9999-061110-a hbwhelp@micrel.com ordering information (1) part number package type operating range package marking lead finish sy100ep14aukg k4-20-1 industrial xep14au with pb-free bar line indicator nipdau pb-free SY100EP14AUKGTR (2) k4-20-1 industrial xep14au with pb-free bar line indicator nipdau pb-free note: 1. contact factory for die availability. dice are guaranteed at ta = 25c, dc electricals only. 2. tape and reel. pin configuration 20-pin tssop
micrel, inc. sy100ep14au june 2010 3 m9999-061110-a hbwhelp@micrel.com pin description pin number pin name pin function 13, 14 16, 17 clk0, /clk0 clk1, /clk1 lvpecl, lvecl, hstl clock or data inputs. internal 75k ? pull-down resistors on clk0, clk1, and internal 75k ? pull-up and 75k ? pull-down resistors on /clk0, /clk1. for single-ended applications, connect signal into clk0 and/or cl k1 inputs. /clk0, /clk1 default condition is v cc /2 when left floating. clk0, clk1 default condition is low when left floating. 1, 2, 3, 4 5, 6, 7, 8 9, 10 q0, /q0, q1, /q1 q2, /q2, q3, /q3 q4, /q4 lvpecl/lvecl differential outputs: terminate with 50 ? to v cc -2v. for single-ended applications, /q0 to /q4 terminate the unused output with 50 ? to v cc -2v. 19 /en lvpecl/lvecl compatible synchronous enable: when /en goes high, the q out will go low and /q out will go high on the next low input clock transition. includes a 75k ? pull-down. default state is low when left floating. the in ternal latch is clocked on the falling edge of the input clock (clk0, clk1). 12 sel lvpecl/lvecl compatible 2:1 mux input signal se lect: when sel is low, clk0 input pair is selected. when sel is high, clk1 input pair is selected. includes a 75k ? pull-down. default state is low and clk0 is selected. 15 vbb output reference voltage: equal to v cc -1.4v (approx.), and used for single-ended input signals or ac-coupled applications. for single-ended lvpecl and lvecl applications, bypass with a 0.01f to v cc. max. sink/source current is 0.5ma. 18, 20 vcc positive power supply: bypass with 0.1f//0.01f low esr capacitors. 11 vee negative power supply: lvpecl applications, connect to gnd. truth table clk0 clk1 clk_sel /en q l x l l l h x l l h x l h l l x h h l h x x x h l note: 1. on next negative transition of clk0 or clk1. function table clk_sel active input 0 clk0, /clk0 1 clk1, /clk1
micrel, inc. sy100ep14au june 2010 4 m9999-061110-a hbwhelp@micrel.com absolute maximum ratings (1) supply voltage (v cc - v ee ) ............................. -0.5v to +4.0v input voltage (v in ) v cc = 0v, v in not more negative than v ee...... -4.0v to 0v v ee = 0v, v in not more positive than v cc....... 0v to +4.0v output current (i out ) continuous............................................................50ma surge ..................................................................100ma lead temperature (solderi ng, 20sec.) ..................... +260c i bb (v bb sink/source current) (3) .............................. 0.5ma storage temperature (t s).........................?65c to +150c operating ratings (2) supply voltage (v in )............................ +2.375v to +3.60v ambient temperature (t a ) .......................?40c to +85c junction thermal resistance ( ja ) still air, single-layer pcb .............................115c/w still air, multi- layer pcb .................................75c/w 500lfpm, multi-la yer pcb ................................65c/w package thermal resistance ( jc ) .................................. 21c/w dc electrical characteristics (4) -40c t a +85c, unless noted. symbol parameter condition min typ max units v cc power supply voltage (lvpecl) 2.37 3.3 3.6 v v ee power supply vo ltage (lvecl) v cc = 0v ?3.6 ?3.3 ?2.37 v i cc power supply current 45 65 ma i ih input high current v in = v ih ? ? 150 a i il input low current d v in = v il 0.5 ? ? a i il input low current /d v in = v il ?150 ? ? a c in input capacitance (tssop) t a = +25c ? 0.75 ? pf notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data shee t. exposure to absolute maximum rating con ditions for extended periods may affect devices reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. due to the limited drive capability, use for inputs of same package only. 4. the circuit is designed to meet the dc specifications shown in the above table a fter thermal equilibrium is established.
micrel, inc. sy100ep14au june 2010 5 m9999-061110-a hbwhelp@micrel.com (100kep) lvpecl dc electrical characteristics (1) v cc = 2.5v 5%, v ee = 0v; -40c t a +85c, unless noted. symbol parameter condition min typ max units v il input low voltage (2) (single-ended) 555 ? 875 mv v ih input high voltage (2) (single-ended) 1335 ? 1620 mv v ol output low voltage 50 ? to v cc ?2v 555 700 900 mv v oh output high voltage 50 ? to v cc ?2v 1355 1480 1605 mv v ihcmr input high voltage common mode range (3) 1.2 ? v cc v (100kep) lvpecl dc el ectrical characteristics (1) v cc = 3.3v 10%, v ee = 0v; -40c t a +85c, unless noted. symbol parameter condition min typ max units v il input low voltage (2) (single-ended) 1355 ? 1675 mv v ih input high voltage (2) (single-ended) 2135 ? 2420 mv v ol output low voltage 50 ? to v cc ?2v 1355 1500 1700 mv v oh output high voltage 50 ? to v cc ?2v 2155 2280 2405 mv v bb reference voltage (2) v cc = 3.3v 1775 1875 1975 mv v ihcmr input high voltage common mode range (3) 1.2 ? v cc v (100kep) lvecl dc elec trical characteristics (1) v ee = ?2.37v to ?3.6v, v cc = 0v; -40c t a +85c, unless noted. symbol parameter condition min typ max units v il input low voltage (singl e-ended) ?1945 ? ?1625 mv v ih input high voltage (single-ended) ?1165 ? ?880 mv v ol output low voltage 50 ? to v cc ?2v ?1945 ?1800 ?1600 mv v oh output high voltage 50 ? to v cc ?2v ?1145 ?1020 ?895 mv v bb output reference voltage (2) ?1525 ?1425 ?1325 mv v ihcmr input high voltage common mode range (3) vee + 1.2 0.0 v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above tabl e after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and traver se airflow greater than 500lfpm is maintained. input and outpu t parameters vary1:1 with v cc . 2. single-ended input operation is limited v ee ?3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
micrel, inc. sy100ep14au june 2010 6 m9999-061110-a hbwhelp@micrel.com hstl input dc electrical characteristics v cc = 2.37v to 3.6v, v ee = 0v symbol parameter condition min typ max units v ih input high voltage 1200 ? ? mv v il input low voltage ? ? 400 mv v x input crossover voltage 680 ? 900 mv ac electrical characteristics lvpecl: v cc = 2.37v to 2.625v, v ee = 0v; lvecl: v ee = ?2.37v to ?3.6v, v cc = 0v; -40c t a +85c, unless noted. symbol parameter condition min typ max units f max maximum frequency (1) 2 ? ? ghz t pd propagation delay to output (differential input) 300 425 550 ps t pd propagation delay to output in (single-ended input) t a = +25c ? 400 ? ps within-device skew (diff.) ? 15 25 ps t skew (2) part-to-part skew (diff.) ? 100 175 ps t s set-up time (3) /en to clk 75 -85 ? ps t h hold time (3) clk to /en 250 95 ? ps t jitter random jitter (rms) (4) ? 0.15 0.3 ps t jitter crosstalk-induced jitter (rms) (5) ? ? 0.7 ps v pp minimum input swing 150 800 1200 mv t r, t f rise and fall time 20% to 80% 80 160 250 ps notes: 1. f max is defined as the maximum toggle frequency. measured with 750mv input signal, 50% duty cycle, all loading with 50 ? to v cc ?2v. 2. skew is measured between ou tputs under identical transitions. 3. set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. for async hronous applications, set-up and hold time does not apply. 4. integration range: 12khz to 20mhz at 1ghz fc. 5. crosstalk is measured at the output while applying two similar differential clock frequencies t hat are asynchronous with res pect to each other at the inputs.
micrel, inc. sy100ep14au june 2010 7 m9999-061110-a hbwhelp@micrel.com termination recommendations figure 1. parallel termination- thevenin equivalent note: for 2.5v systems: r1= 250 ? , r2= 62.5 ? figure 2. three-resistor ?y-termination? notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as clos e to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . for 3.3v systems r b =50 ? . figure 3. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel?s differential i/o logic devices include a v bb reference pin. 3. connect unused input through 50 ? to v bb . bypass with a 0.01f capacitor to v cc , not gnd. 4. for 2.5v systems: r1= 250 ? , r2= 62.5 ? .
micrel, inc. sy100ep14au june 2010 8 m9999-061110-a hbwhelp@micrel.com package information 20-pin tssop (k4-20-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incorporated.
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